|
Size: 685
Comment:
|
Size: 830
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 2: | Line 2: |
| [[TableOfContents(3)]] | |
| Line 3: | Line 4: |
| == Les Cours Verilog == | = COURS = == Verilog == http://www.comelec.enst.fr/hdl == Architectures == attachment:ARCHI.pdf |
| Line 5: | Line 10: |
| [:/TdFiltreMedian:TD1 Verilog : Le filtre Median] | |
| Line 7: | Line 11: |
| == Les cours sur le processeur ARM == | = TDs = == Verilog == [:/TdFiltreMedian:TD Verilog : Le filtre Median] =http://www.comelec.enst.fr/amen/SMLP/TPs/verilog/index.html == carte ARM == |
| Line 15: | Line 23: |
| == Les Cours sur la maquette DE2 == | == carte FPGA == |
COURS
Verilog
http://www.comelec.enst.fr/hdl
Architectures
attachment:ARCHI.pdf
TDs
Verilog
[:/TdFiltreMedian:TD Verilog : Le filtre Median] =http://www.comelec.enst.fr/amen/SMLP/TPs/verilog/index.html
carte ARM
[:/ArmTD1:TD1 : Prise en main de la maquette ARM FS44BOXII]
[:/ArmTD2:TD2 : Etude de l'interface "ATA" de la maquette ARM FS44BOXII]
[:/MaquetteArm: Gestion de la Maquette ARM FS44BOXII]
carte FPGA
[:/De2TD1:TD1 : Prise en main de la maquette ALTERA DE2]
[:/De2TD2:TD2 : Réalisation d'une interface entre FS44BOXII/DE2 via l'interface "ATA"]
[:/De2Doc: Documentations de la carte ALTERA DE2]
Administration
[:/LesProjets: Les projets]