edge_clock posedge
instream_boundary_fifo never
stream_boundary_fifo never
headers fir.h fixed_point.h
memory_return_path_external_delay 60%
cpp_compiler gcc
memory_forward_path_external_delay 60%
last_set_use_command set_experiment_params
ccompiler_args -g
instream_forward_path_external_delay 60%
flex_version none
vcs:vexec_args +vcs+lic+wait
outstream_return_path_external_delay 60%
ncv:vexec_args +nclicqueue
npa_c_file fir.c
reset_level high
hostlm_memory_mode inferred
proc_name fir
sources driver.c fir.c fixed_point.c
memory_forward_boundary_register always
reset_sensitivity sync
interface_type pure_memory
cppcompiler_args -g
rom_synthesis_threshold 256:4096
MITI 0
raw_liveinout_mode specified
ram_synthesis_threshold 16:256
auto_refresh_reports yes
techlib_path synopsys_dcultra_synopsys_tsmc090ghpwc
memory_return_boundary_register always
experiment_creation_time Mon Mar 19 10:58:32 PM UTC 2007
memory_external_delay_constraint 60
stream_external_delay_constraint 60
base_address 0x10000
name default
init_data_registers no
outstream_forward_path_external_delay 60%
hostlm_access_latency minimal
max_task_frame 1
results x.dat y2.dat y3.dat
outstream_boundary_fifo never
reset_data_registers yes
c_compiler gcc
instream_return_path_external_delay 60%
vlog_simulator modelsim
memory_boundary_register always
clock_freq 100
clinker_args -lm
